In the literature, Improved Recycling Folded Cascode (IRFC) Operational Transconductance Amplifier (OTA) is proposed for enhancing the DC gain and the Unity Gain Bandwidth (UGB) of the Recycling Folded Cascode (RFC) OTA. In this paper, an enhanced IRFC (EIRFC) OTA which uses positive feedback at the cascode node is proposed for enhancing the differential mode (DM) gain without changing the unit...

In order to achieve an overall noise of less than 1000 electrons per channel for a typical input capacitance of a total of 5-10 pF, the use of a low-noise circuit is required. A well proven topology to fulfil such a requirement is shown in fig. 1. Each channel consist of a low noise chargesensitive amplifier, an active CR-(RC) pulse shaper. The main noise contributor is the input transistor of ...

An optimum OTA topology is done in order to optimize MOS transistor sizing.Also, the design of folded cascode OTA, which works for frequencies that lead to a base band circuit design for RF application, is based on transistor sizing methodology. Simulation results are performed using SPICE software and BSIM3V3 model for CMOS 0.18μm process, show that the designed folded cascode OTA has a 52dB D...

This thesis describes work done towards realizing self-aligned AlGaN/GaN high electron mobility transistors (HEMTs). Self-aligned transistors are important for improving the frequency of AlGaN/GaN HEMTs by reducing source and drain access resistance. The eventual fabrication of self-aligned transistors required the development of two different technologies that are described in this thesis. Fir...

High-resolution high-speed comparators are one of the main cores in the implementation of the high-performance systems, such as ADCs. Two comparators are presented in this paper where both of the structures are suitable for high-speed, low-noise and accurate applications. The comparators are designed, based on the positive feedback structure of two back-to-back inverters. An improved rail-to-ra...

A wide swing charge sensitive amplifier (CSA) has been developed, as a part of front-end electronics (FEE) readout ASIC, for prototype silicon tungsten (Si-W) based electromagnetic (EM) calorimeter. The CSA, designed in 0.35 $\mu$m N-well CMOS technology using 5V MOS transistors, linear operating range 2.6 pC w.r.t the input with power dissipation 2.3 mW. noise figure (ENC) 820 e$^-$ at 0 pF de...

In this article, we report on the modeling, design, and characterization of indium phosphide (InP) double heterojunction bipolar transistor (DHBT) devices integrated circuits (ICs) for next-generation optical communications. Critical aspects transistors’ modeling their influence IC design are detailed, as well a lumped linear modulator driver featuring 3-Vppd four-level pulse-amplitude modulati...

it has been recently shown that manufacturing p-n-junctions, field-effect and bipolar transistors, thyristors in a multilayer structure by diffusion or ion implantation with the optimization of dopant and/or radiation defects leads to increase the sharpness of p-n-junctions (both single p-n-junctions and p-n-junctions framework their system). due to the optimization, one can also obtain increas...

In this work, we present atomic scale simulation of junctionless semiconducting single–walled carbon nanotubes field effect transistors (CNT–FETs) and compare their performance to silicon nanowire (SiNW) transistors with similar dimensions. The energy dispersions relations for p–type SiNW and CNT are compared. The response of the transistors to source–drain bias and gate voltage is explored. Co...