Host-based mobility and multi-homing protocols allow hosts to migrate ongoing transport sessions between networks or network interfaces. While such protocols can facilitate vertical mobility in a cost-efficient and accessagnostic manner, they are hard to secure when strong authentication between end points is not available. We present a balanced security solution which protects these protocols ...

Mobile IPv6, also known as MIPv6, is an IETF standard that has added the roaming capabilities of Mobile Nodes (MNs) in IPv6 network. It allows an MN to move from one network to another without any disruption in communication. The MN registers its current location to the Home Agent (HA) and the Correspondent Node (CN) with the help of a secure Binding Update (BU). Return Routability Protocol (RR...

We consider the problem of one-dimensional topological com-paction with jog insertions. Combining both geometric and graph the-oretic approaches we present a faster and simpler algorithm, improving over previous results. The compaction algorithm takes as input a sketch consisting of a set F of features and a set W of wires, and minimizes the horizontal width of the sketch while maintaining its ...

For a four-layer datapath routing environment, we present an algorithm that considers all the nets simultaneously, thus avoiding the net-ordering problem. Our algorithm progresses in two phases. The first phase involves formulating the problem using a probabilistic model, whereby routing probabilities are calculated for potential routing regions; these probabilities are consolidated into a cong...

Asynchronous serial transceivers have been recently used for data serializing in large on-chip systems to alleviate the routing congestion and improve the routability. FPGAs have considerable potential for using the asynchronous serial transmission but they have serious challenges to use this technology. In this paper, we present a new FPGA architecture corresponding with a new routing algorith...

Field-programmable gate arrays (FPGAs) are becoming an increasingly important implementation medium for digital logic. One of the most important keys to using FPGAs effectively is a complete, automated software system for mapping onto the FPGA architecture. Unfortunately, many of the tools necessary require different techniques than traditional circuit implementation options, and these techniqu...

A survey of Field-Programmable Gate Array (FPGA) architectures and the programming technologies used to customize them is presented. Programming technologies are compared on the basis of their vola fility, size, parasitic capacitance, resistance, and process technology complexity. FPGA architectures are divided into two constituents: logic block architectures and routing architectures. A classi...

This paper describes the Transmogrifier-2 (TM-2), a second-generation multifield programmable gate array (FPGA) rapid-prototyping system. The largest version of the system will comprise 16 boards that each contain two Altera 10K50 FPGA’s, four I-Cube interconnect chips, and up to 8 Mbytes of memory. The inter-FPGA routing architecture of the TM-2 uses a novel interconnect structure, a nonunifor...

With the continuing advances of VLSI-technology, multiple layer channel routing has become increasingly important. A new n-layer gridless channel router is presented. Instead of the commonly employed grid it uses a set of contours as routing framework. The contours together with a set of reserved areas prevent short circuits and ensure routability of all nets. A compact routing can he expected ...

The increment of transistors inside one chip has been following Moore’s Law. To cope with dense chip design for VLSI systems, a new routing paradigm, called X-Architecture, is introduced. In this paper, we present novel resources estimation and routability models for standard cell global routing in X-Architecture. By using these models, we route the chip with a compensationbased convergent appr...