Leading digital circuits namely register, flipflops, state machines and counters drive operational aspects potential applications in Integrated Circuit (IC) industry. MOS Current Mode Logic (MCML) based implementations with rapid response simultaneous generation of complemented output is all set to become indispensable nano regime This paper attempts optimize address performance-based analysis ...

Dynamic logic style is used in high performance circuit design because of its fast speed and less transistors requirement as compared to CMOS logic style. But it is not widely accepted for all types of circuit implementations due to its less noise tolerance and charge sharing problems. A small noise at the input of the dynamic logic can change the desired output. Domino logic uses one static CM...

This paper discusses a rail to rail swing, mixed logic style 1-bit 28-transistor (28T) full-adder, based on a novel architecture. The performance metrics: power, delay, and power delay product (PDP) of the proposed 1-bit adder is compared with other two high performance 1-bit adder architectures reported, till date. The proposed 1-bit adder has a 50% improvement in delay, and 49% improvement in...

This literature illustrates the high speed and low power Full Adder (FADD) designs. study relates to composited structure of FADD design composed in one unit. In this EXCL-OR/EXCL-NOR designs are used FADD. Mostly concentrates on standard by combining single We implemented two composite structures through full swing And is done pass transistor logic (PTL) same projected design. Such that delay,...

Multiple-Valued Logic systems present significant improvements in terms of energy consumption over binary logic systems. This paper proposes new ternary combinational digital circuits that reduce low-power nano-scale embedded and Internet Thing (IoT) devices to save their battery consumption. The 32 nm CNTFET-based half adder (THA) multiplier (TMUL) use novel unary operator implement two power ...

<span lang="EN-US">In many signal processing applications, multiplier is an important functional block that plays a crucial role in computation. It always challenging task to design the delay optimized at system level. A new and delay-efficient structure for 4:3 counter proposed by making use of two-bit reordering circuit. The along with 7:3 counter, full adder (FA), half (HA) circuits ar...

The Content Addressable Memory (CAM) is a class of memory that allows access by data instead of by physical address. On a read access to a CAM, embedded into a processor cache, each word is compared in a broadcast mode, to see if it matches the requested data; thus requiring only one access. Due to their parallel pattern matching property, CAMs are gaining increasing importance over Random Acce...

This article explores the main tradeoffs in design of subthreshold source-couple logic (STSCL) circuits. It is shown analytically that the bias current of each STSCL gate can be reduced to few pico-amperes with a reliable logic operation. Measurements on different digital building blocks are provided to validate the main concepts presented in this paper. Implemented in conventional 0.18μm CMOS ...

Two novel low-power 1-bit Full Adder cells are proposed in this paper. Both of them are based on majority-not gates, which are designed with new methods in each cell. The first cell is only composed of input capacitors and CMOS inverters, and the second one also takes advantage of a high-performance CMOS bridge circuit. These kinds of designs enjoy low power consumption, a high degree of regula...