Planar MOS devices miniaturization becomes quite challenging for transistors with reduced channel length due to the loss of gate control over the channel charges. As an alternative, multi-gate devices have been developed due to the better electrostatic control of the charges, which leads to a reduction of the short-channel effects [1-6]. However, for devices with extremely reduced channel lengt...

Abstract In this study, we developed a capacitorless dynamic random-access memory (DRAM) (1T-DRAM) device based on junctionless (JL) bulk-fin field-effect transistor structure with excellent reliability and negligible variability against work-function variation (WFV). We investigated the in transfer characteristics performance of cell owing to WFV. particular, investigate WFV effect, analyzed 2...

Abstract In this work, the memory characteristics of oxide–semiconductor (OS) channel antiferroelectric FETs (AFeFETs) are investigated by developing a compact model AFeFETs. The consists an analytic junctionless FeFET and newly developed AFe Preisach model. can reproduce arbitrary minor loop measurement results. key feature AFeFETs is using half-loop hysteresis in contrast to full Fe. Only sma...

This study investigates geometrical variability on the sensitivity of the junctionless tunneling field effect transistor (JLTFET) and Heterostructure JLTFET (HJLTFET) performance. We consider the transistor gate dielectric thickness as one of the main variation sources. The impacts of variations on the analog and digital performance of the devices are calculated by using computer aided design (...