As field programmable gate array (FPGA) technology has steadily improved, FPGAs have become viable alternatives to other technology implementations for high-speed classes of digital signal processing (DSP) applications. In particular, radar front-end signal processing, an application formerly dominated by custom very large scale integration (VLSI) chips, may now be a prime candidate for migrati...

Local search methods such as WSAT have proven to be successful for solving SAT problems. In this paper, we propose two host-FPGA (Field Programmable Gate Array) co-implementations, which use modified WSAT algorithms to solve SAT problems. Our implementations are reconfigurable in real-time for different problem instances. On an XCV1000 FPGA chip, SAT problems up to 100 variables and 220 clauses...

Current FPGAs are heterogeneous partially reconfigurable architectures, consisting of several resource types, e. g., logic cells and embedded memory. By using partial reconfiguration, arbitrary hardware tasks can be placed and removed at run-time, causing the free FPGA resources to become fragmented over time. This fragmentation can prevent a requested task from being placed, if the required FP...

Industrial process control is an untapped market for field programmable gate arrays (FPGAs). Programs used for industrial process control are traditionally written in a graphical language called relay ladder logic, and implemented on programmable logic controllers (PLCs). The mapping of ladder logic onto typical FPGAs is a lengthy process, and results are hard to verib. We propose an FPGA archi...

Recently, there has been a renewal of interest in self-timed systems, due to their modularity, robustness, low-power consumption and average-case performance. Additionally, this paper argues that there are speciic beneets to adopting self-timed design for FPGAs. The mapping problems of placement, routing and partitioning are simpliied by not having a global clock constraint to meet, so more map...

Shrinking size of transistors has enabled us to integrate more and more logic elements into FPGA chips leading to higher computing power. However, it also brings a serious concern to the leakage power dissipation of the FPGA devices. One of the major reasons for leakage power dissipation in FPGA is the utilization of prefetching technique to minimize the reconfiguration overhead (delay) in Part...

The FPGA can be reconfigured both dynamically and partially. Such reconfigurable FPGA allows several tasks to be executed, placed and removed at the runtime. Therefore, the hardware resources management in FPGA on the online placement becomes very important. Most techniques for finding empty space are based on rectangle. In this paper, we propose an adaptive free space management for finding ca...

The Realizer is a logic emulation system that automatically configures a network of Field-Programmble Gate Arrays (FPGA’s) to implement large digital logic designs. Logic and interconnect are separated to achieve optimum FPGA utilization. Its interconnection architecture, called the partial crossbar, greatly reduces system-level placement and routing complexity, achieves bounded interconnect de...

Sequential place and route tools for field programmable gate arrays (FPGA’s) are inherently weak at addressing both wirability and timing optimizations. This is primarily due to the difficulty of accurately predicting wirability and delay during placement. A set of new performancedriven simultaneous placement/routing techniques has been developed for both row-based and island-style FPGA designs...

SUMMARY In this thesis we study the possibility of using logic replication in order to improve timing performance in VLSI design. In particular, we restrict our analysis to FPGA architectures. We describe an algorithm for post-placement timing optimization that exploits the additional freedom degree of logic duplication.