Physical Design is a complex CAD topic, which is difficult to teach to electrical and computer engineers. I have developed a complete skeleton for teaching basic algorithms such as Fiduccia-Mattheyses partitioning, variable node size sliceable floorplanning, simulated annealing placement, maze router based global routing, and left-edge algorithm channel routing. The Java-based toolset is portab...

Description: The objective of the tutorial is to survey recent algorithms and methodologies that have had (or are likely to have) a significant impact on the physical design industry. A second objective is to provide industrial feedback to the academic community in an effort to increase the relevance of academic research to industrial needs. Outline: Data Structures for VLSI, Partitioning, Floo...

3-D IC technologies have recently drawn great interest due to their potential performance improvement, power consumption reduction and heterogeneous components integration. One of the largest challenges in 3-D IC design is heat dissipation. In this paper we propose a thermal-aware physical design process for 3-D ICs, including floorplanning (3DFP-T), placement (T3Place) and routing (TMARS). Tem...

This paper presents a hierarchical oorplanning approach for macrocell layouts which is based on the bottom up clustering shape function computation and top down oor plan optimization with integrated global routing and pin assignment This approach provides means for specifying and techniques for satisfying a wide range of constraints physical topological timing and is therefore able to generate ...

Abstract The floorplanning (or facility layout) problem consists in finding the optimal positions for a given set of modules of fixed area (but perhaps varying height and width) within a facility such that the distances between pairs of modules that have a positive connection cost are minimized. This is a hard combinatorial optimization problem; even the restricted version where the shapes of t...

Classical floorplanning minimizes a linear combination of area and wirelength. When Simulated Annealing is used, e.g., with the Sequence Pair representation, the typical choice of moves is fairly straightforward. In this work, we study the fixed-outline floorplan formulation that is more relevant to hierarchical design style and is justified for very large ASICs and SoCs. We empirically show th...

Backside light emission and electrical measurements were used to evaluate the susceptibility to latchup of externally cabled I/O pins for a 0.13 μm technology generation [1,2] test chip, which was designed in a flip-chip package. Case studies of several Inputs/Outputs (I/Os) are shown along with conclusions regarding layout and floorplanning to ensure the robustness to various types of latchup ...

An integrated standard-cell physical design algorithm (ISCPD) is presented. A spine net topology is adopted, enabling quick construction of the placement and routing of a standard-cell design with guaranteed routability. Experiments show that ISCPD is comparable to commercial placement and routing tools in terms of area and wire length but several times faster, making it very suitable for physi...

This thesis presents efficient algorithms for drawing planar graphs. Graph drawing addresses the problem of constructing geometric representation of information and finds applications in almost every branch of science and technology. In this thesis we study rectangular drawings, orthogonal drawings, convex drawings and our newly defined box-rectangular drawings. Rectangular drawings and box-rec...