The first inversion-mode gate-all-around (GAA) III-V MOSFETs are experimentally demonstrated with a high mobility In0.53Ga0.47As channel and atomic-layer-deposited (ALD) Al2O3/WN gate stacks by a top-down approach. A wellcontrolled InGaAs nanowire release process and a novel ALD high-k/metal gate process has been developed to enable the fabrication of III-V GAA MOSFETs. Well-behaved on-state an...

A process of making a symmetrical self-aligned n-type vertical double-gate MOSFET (nVDGM) over a silicon pillar is revealed. This process utilizes the technique of oblique rotating ion implantation (ORI). The self-aligned region forms a sharp vertical channel profile and decreases the channel length Lg. A tremendous improvement in the drive-on current is noted. The electron concentration profil...

In the light of a modified two-dimensional Poisson equation, an analytical model for the threshold voltage Vth of deep-submicrometre MOSFETs is developed, which can show Vth’s nonlinear dependence on drain voltage Vds . Meanwhile, by introducing a normalized effective gate voltage Vgtx to obtain continuous channel charge characteristics from the subthreshold to the strong inversion region and p...

In this paper, we compare four SRAM circuits. They are the conventional SRAM1, the SRAM2 with power switches on VSS line, the SRAM3 with switches on VDD line, and the SRAM4 with switches on both VDD and VSS lines, respectively. Among the four SRAMs, the SRAM2 shows the smallest amount of leakage, because its subthreshold leakage is most suppressed by its BODY and Drain-Induced Barrier Lowering ...

In this paper, we have investigated the effect of a single Grain Boundary (GB) on the performance of decananometer-scale Thin Film Transistors (TFTs) by using the calibrated energy balance transport model and a continuous trap state distribution at the GB. We have found that the GB potential barrier suppresses the subthreshold slope and leakage current in devices, where the DIBL effect and punc...

This paper presents a closed-form compact model for the undoped double-gate (DG) MOSFET under symmetrical operation. This charge-based model aims at giving a comprehensive understanding of the device from the circuit design point of view. Both static and dynamic models are derived in terms of simple analytic relationships based on our new explicit formulation of the mobile charge density. Our a...

Received April 27, 2012 Revised May 14, 2012 Accepted May 26, 2012 Application of symmetric double gate vertical metal oxide semiconductor field effect transistors (MOSFETs) is hindered by the parasitic overlap capacitance associated with their layout, which is considerably larger than for a lateral MOSFET on the same technology node. A simple process simulation has been developed to reduce the...

An InAlAs/InGaAs HEMT with an InAs-rich barrier spacer (In0.52Al0.48As) to reduce the parasitic resistance is reported. Devices were obtained with a source resistance of 170 V-mm. A 40 nm gate length In0.7Ga0.3As HEMT with Lside 1⁄4 100 nm and tins 1⁄4 10 nm shows excellent transconductance and subthreshold characteristics including gm 1⁄4 1.6 mS/mm, DIBL 1⁄4 122 mV/V and S 1⁄4 80 mV/ dec at VD...

We present a modeling scheme for simulating ballistic hole transport in thin-body fully depleted silicon-on-insulator pMOSFETs. The scheme includes all of the quantum effects associated with hole confinement and also accounts for valence band nonparabolicity approximately. This simulator is used to examine the effects of hole quantization on device performance by simulating a thin (1.5-nm) and ...