Logic Cell modeling is an important component in the analysis and design of CMOS integrated circuits, mostly due to nonlinear behavior of CMOS cells with respect to the voltage signal at their input and output pins. A current-based model for CMOS logic cells is presented which can be used for effective crosstalk noise and delta delay analysis in CMOS VLSI circuits. Existing current source model...

An experimental methodology to find area-efficient compact layout rules to prevent latchup in bulk complimentary metal–oxide–semiconductor (CMOS) integrated circuits (ICs) is proposed. The layout rules are extracted from the test patterns with different layout spacings or distances. A new latchup prevention design by adding the additional internal double guard rings between input/output cells a...

This paper presents an investigation of noise figure optimization techniques for a 915 MHz CMOS Low Noise Amplifier (LNA). The research’s goal is to evaluate the trade off between fully and partially integrated solutions for 915 MHz CMOS LNA. The analysis considers an inductively source-degenerated cascode topology, which is capable of achieving simultaneous noise and input match, with narrow b...

A novel electrostatic discharge (ESD) protection device with a threshold voltage of 0V for complementary metal-oxide semiconductor (CMOS) integrated circuits in sub-quarter-micron CMOS technology is proposed. Quite different to the traditional ESD protection devices, such an active ESD device is originally standing in its turn-on state when the IC is zapped under ESD events. Therefore, such an ...

This paper deals with the design and performance analysis of a ring oscillator using CMOS 45nm technology process in Cadence virtuoso environment. The design of optimal Analog and Mixed Signal (AMS) very large scale integrated circuits (VLSI) is a challenging task for the integrated circuit(IC) designer. A Ring Oscillator is an active device which is made up of odd number of NOT gates and whose...

This paper discusses some of the advantages and of the disadvantages of using a CMOS process in the 180 – 100 nm range for the design of analog blocks in mixed-mode integrated circuits.

In mixed-signal designs, substrate coupling of digital circuit noise can severely compromise the behavior of sensitive analog circuits. Proper characterization of substrate noise is therefore indispensable. In this paper, we present an experimental setup for the characterization of directly coupled substrate noise in bulk-type CMOS. We have integrated configurable substrate noise generation and...

The future interconnect links in intra- and inter-chip require the photodetector with high bandwidth, ultra-wide waveband, compact footprint, low-cost, compatible integration process silicon complementary metal-oxide-semiconductor (CMOS) technology. Here, we demonstrate a CMOS-compatible carbon nanotube (CNT) that exhibits responsivity, bandwidth broad spectral operation over all optical teleco...

In this thesis three novel analog techniques for testing CMOS Integrated circuits are presented. These techniques are based on analog circuits since they offer a number of important advantages compared to standard digital test techniques, such us less silicon area, lower power consumption and high operating speed. Therefore, the proposed techniques can be embedded in the circuit under test, con...

The integrated circuit revolution has impacted virtually all fields of engineering. The main driving force behind this revolution is Complementary Metal-Oxide Semiconductor (CMOS) transistor technology. As CMOS integrated circuit “chips” have come to dominate analog and digital electronics, introductory electronics courses in Electrical and Computer Engineering programs have evolved to place gr...