metal oxide surge arrester accurate modeling and its parameter identification are very important for insulation coordination studies, arrester allocation and system reliability. since quality and reliability of lightning performance studies can be improved with the more efficient representation of the arresters´ dynamic behavior. in this paper, big bang – big crunch and hybrid big bang – big cr...

The short and long term reliability of National Semiconductor’s interface circuits, like any integrated circuit, is very dependent on its environmental condition. Beyond the mechanical/environmental factors, nothing has a greater influence on this reliability than the electrical and thermal stress seen by the integrated circuit. Both of these stress issues are specifically addressed on every in...

PURPOSE To assess the validity and reliability of distance data measured by global positioning system (GPS) units sampling at 1 and 5 Hz during movement patterns common to team sports. METHODS Twenty elite Australian Football players each wearing two GPS devices (MinimaxX, Catapult, Australia) completed straight line movements (10, 20, 40 m) at various speeds (walk, jog, stride, sprint), chan...

Double-gate fully depleted (DGFD) SOI circuits are regarded as the next generation VLSI circuits. This paper investigates the impact of scaling on the demand and challenges of DGFD SOI circuit design for low power and high performance. We study how the added back-gate capacitance affects circuit power and performance; how to tradeoff the enhanced short-channel effect immunity with the added bac...

This paper presents the development methodology, circuit realization and measurement of a cryptographic core intended to operate reliably in the presence of massive defect density. A circuit-level voter based on averaging and thresholding has been implemented, and is measured to offer superior reliability in comparison with standard techniques.

Failure of blind via is one of the main causes of an open circuit in printed circuit boards (PCBs). By using macroscopic and microscopic testing methods and characterization techniques, the failure analysis of the vias on PCB for novel mobile phones has been systematically carried out. Metallographic inspection shows obvious cracking along the interface of different copper layers. Micrograph ob...

The same defects that degrade device yield also affect device reliability. The complete theory is complicated and depends on factors such as die size, defect density, defect size distribution, circuit layout density, and environmental stress. We analyze the simplifying assumptions necessary for a practical model. Then we show how to use the practical model to extract process-specific reliabilit...

Design, Analysis and Test of Logic Circuits under Uncertainty bySmita Krishnaswamy Co-Chairs: John P. Hayes and Igor L. Markov Integrated circuits (ICs) are increasingly susceptible to uncertainty caused by softerrors, inherently probabilistic devices, and manufacturing variability. As device tech-nologies scale, these effects become detrimental to circuit reliability. In order to a...

Traditionally the position of reliability analysis in the design and production process of electronic circuits is a position of reliability verification. A completed design is checked on reliability aspects and either rejected or accepted for production. This paper describes a method to model physical failure mechanisms within components in such a way that they can be used for reliability optim...

As new technologies use a reduced transistor size to improve performance, circuits are becoming remarkably sensitive to soft errors that become a serious threat for critical applications reliability. Most of the existing reliability enhancing techniques lead to costly hardware. The masking phenomenon is fundamental to accurately estimating soft error rates (SER). The first contribution of this ...