Low Complexity and High speed in Leading DCD ERLS Algorithm

Adaptive algorithms lead to adjust the system coefficients based on the measured data. This paper presents a dichotomous coordinate descent method to reduce the computational complexity and to improve the tracking ability based on the variable forgetting factor when there are a lot of changes in the system. Vedic mathematics is used to implement the multiplier and the divider in the VFF equations, to improve the area and to increase the computational speed. The linear Exponentially Weighted Recursive Least Squares as the main algorithm in the system can be implemented in the adaptive controller, the system identification, active noise cancellation techniques, and etc. The DCD method calculates the inverse matrix in the ERLS algorithm and decreases the used resources in a field-programmable gate array, also the designer can use the cheaper FPGA board to implement the adaptive algorithm because the design doesn't need high resources. The proposed method leads to implement complex algorithms with simple structures and high technology. This method is implemented with ISE software on the Spartan 6 Xilinx board. The proposed algorithm calculates the result multiplication with less than 15ns and reduces the used FPGA resources to lower than 20% compared to the classic RLS.