GPS Time Reception Using Altera SOPC Builder and Nios II: Application in Train Positioning

gps time reception using altera sopc builder and nios ii: application in train positioning

as functional integration has increased in hand-held consumer devices features such as global positioning system (gps) receivers have been embedded in increasingly more devices in recent years. for example, the train positioning system based on gps provides an integrated positioning solution which can be used in many rail applications without a cost intensive infrastructure. the network built i...

Embedded Sopc Design with Nios Ii Processor and Vhdl Examples

Edge Detection Using SOPC Builder and DSP Builder Tool Flow

Introduction Video and image processing applications are typically very computationally intensive. Given the increasing processing demands, the parallel processing capabilities of Altera® programmable logic devices make them an attractive implementation option for highly repetitive tasks found in video and imaging functions. Instead of using multiple programmable digital signal processors, a si...

ERIKA Enterprise Manual for the Altera Nios II target the multicore RTOS on FPGAs

Evidence is a spin-off company of the ReTiS Lab of the Scuola Superiore S. Anna, Pisa, Italy. We are experts in the domain of embedded and real-time systems with a deep knowledge of the design and specification of embedded SW. We keep providing signicant advances in the state of the art of real-time analysis and multiprocessor scheduling. Our methodologies and tools aim at bringing innovative s...

Montgomery Multiplication Coprocessor for Altera NIOS Embedded Processor

This paper describes scalable Montgomery Multiplication (MM) coprocessor optimized for Altera NIOS embedded processor implemented in reconfigurable hardware. Features of the NIOS soft processor Avalon Bus are used to connect the coprocessor as a memory mapped peripheral so that the overall performance is improved. Implemented coprocessor performs modular MM with large numbers (up to 4096 bits),...

Multimedia Decoder Using the Nios II Processor

Design Introduction Our design target was to build a low-cost, high-performance H.264 decoder with a prototype H.264 decoder created using multiple small FPGAs. H.264 is a computationally complex, advanced video standard for achieving high compression ratios. To cater to the needs of high throughput applications such as HDTV, which requires 216,000 macroblocks/second of throughput, designers us...