Secure FPGA Design by Filling Unused Spaces
Authors
Abstract:
Nowadays there are different kinds of attacks on Field Programmable Gate Array (FPGA). As FPGAs are used in many different applications, its security becomes an important concern, especially in Internet of Things (IoT) applications. Hardware Trojan Horse (HTH) insertion is one of the major security threats that can be implemented in unused space of the FPGA. This unused space is unavoidable to meet the place and route requirements. In this paper, we introduce an efficient method to fill this space and thus to leave no free space for inserting HTHs. Using a shift register in combination with gate-chain is the best way of filling unused space, which incurs a no increase in power consumption of the main design. Experimental results of implementing a set of IWLS benchmarks on Xilinx Virtex devices show that the proposed prevention and detection scheme imposes a no power overhead with no degradation to performance and critical path delay of the main design
similar resources
FPGA Based Secure System Design-an Overview
The implementation of cryptographic algorithm on FPGA is highly addressed in different forums due to its paramount advantages over the other platforms. Most of the secure systems are designed using SRAM based FPGAs with additional security features provided by the manufactures. In this paper, firstly, attempts are made to address different security problems of FPGA based secure systems. The dif...
full textFPGA Fault Injection Platform for Secure Device Design Evaluation
In this paper, we describe our current work on developing tools for experimental evaluation of the efficiency of implemented countermeasures against differential fault attacks on cryptographic cores in the FPGA based systems. The developed fault injection platform enables us to analyze the impact of injected faults at the selected points of the FPGA in its run time operation. In its compact ver...
full textDesign and FPGA Implementation of Secure Key Management
Cryptographic device ensures the secure information exchange and private authentication even in the face of various attacks. In this paper, we focus on how to prevent physical attacks and present the PUF-based security secret-key generation architecture. We develop a novel Spread PUF architecture that is more secured and has higher performance than existing PUF architectures. Our thesis also gi...
full textSynthesis of Secure FPGA Implementations
This paper describes the synthesis of Dynamic Differential Logic to increase the resistance of FPGA implementations against Differential Power Analysis. The synthesis procedure is developed and a detailed description is given of how EDA tools should be used appropriately to implement a secure digital design flow. Compared with an existing technique to implement Dynamic Differential Logic on FPG...
full textSecure FPGA as a Service - Towards Secure Data Processing by Physicalizing the Cloud
Securely processing data in the cloud is still a difficult problem, even with homomorphic encryption and other privacy preserving schemes. Hardware solutions provide additional layers of security and greater performance over their software alternatives. However by definition the cloud should be flexible and adaptive, often viewed as abstracting services from products. By creating services relia...
full textMy Resources
Journal title
volume 11 issue 1
pages 47- 56
publication date 2019-01-30
By following a journal you will be notified via email when a new issue of this journal is published.
Hosted on Doprax cloud platform doprax.com
copyright © 2015-2023