Low-Power Adder Design for Nano-Scale CMOS
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Abstract:
A fast low-power 1-bit full adder circuit suitable for nano-scale CMOS implementation is presented. Out of the three modules in a common full-adder circuit, we have replaced one with a new design, and optimized another one, all with the goal to reduce the static power consumption. The design has been simulated and evaluated using the 65 nm PTM models.
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Journal title
volume 5 issue 3
pages 180- 184
publication date 2009-09
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