Device and Circuit Performance Simulation of a New Nano- Scaled Side Contacted Field Effect Diode Structure

A new side-contacted field effect diode (S-FED) structure has beenintroduced as a modified S-FED, which is composed of a diode and planar double gateMOSFET. In this paper, drain current of modified and conventional S-FEDs wereinvestigated in on-state and off-state. For the conventional S-FED, the potential barrierheight between the source and the channel is observed to become larger and the flow ofinjected electrons is reduced. Thus, the drain current decreases in on-state. While in offstate,the potential barrier height and width become smaller in conventional S-FED andso the drain current is greater than that of modified structure. Mixed mode simulationswere used to determine the performance of the proposed logic gates. We compared theoperation of modified S-FED with that of conventional S-FED. Simulated power delayproduct (PDP) of the modified S-FED-based NOR, NAND, XOR gates were found tobe about 416fJ, 408fJ and 336fJ, respectively, compared with 906fJ, 810fJ and 705fJachievable with conventional S-FED logic gates.