Design and Simulation of a 2GHz, 64×64 bit Arithmetic Logic Unit in 130nm CMOS Technology

The purpose of this paper is to design a 64×64 bit low power, low delay and high speed Arithmetic Logic Unit (ALU). Arithmetic Logic Unit performs arithmetic operation like addition, multiplication. Adders play important role in ALU. For designing adder, the combination of carry lookahead adder and carry select adder, also add-one circuit have been used to achieve high speed and low area. In multiplier design, Booth algorithm and Wallace tree structure have been used. The proposed multiplier is based on Pipeline technique. In Wallace structure, compressors are used for partial product accumulation. By use of booth algorithm to generate partial product, speed of pipeline multiplier has been improved. Achieved delay and power consumption for 64 bit adder under supply voltage of 1.3V and 2GHz frequency are 112ps and 12mw, respectively and for multiplier, delay and power consumption are 291ps and 950mw. The presented structures have been implemented in TSMC 130nm CMOS technology.