An efficient CAD tool for High-Level Synthesis of VLSI digital transformers

Digital transformers are considered as one of the digital circuits being widely used in signal and data processing systems, audio and video processing, medical signal processing as well as telecommunication systems. Transforms such as Discrete Cosine Transform (DCT), Discrete Wavelet Transform (DWT) and Fast Fourier Transform (FFT) are among the ones being commonly used in this area. As an illustration, the DCT is employed in compressing the images. Moreover, the FFT can be utilized in separating the signal spectrum in signal processing systems as fast as possible. The DWT is as well used in separating the signal spectrum in a variety of applications from signal processing to telecommunication systems. In order to build a VLSI circuit, several steps have to be taken from chip design to final construction. The first step in the synthesis of the integrated circuits is called high-level synthesis (HLS), in which a structural characteristic is obtained from a behavioral or algorithmic description. The resulting structural characteristic is equivalent to the one being considered in the behavioral description and it somehow represents the method for implementing the behavioral description so that several structural descriptions could be implementable for each behavioral description. Therefore, depending on the intended use, the characteristic will be selected that outperforms the others. The main purpose of the HLS is to optimize the power consumption, the chip occupied area and delay and this is fulfilled by selecting the appropriate number of operating units and how they are implemented to the operators. This is generally accomplished through a graph analysis called the data flow graph (DFG) which is a graphical representation of the type and how the operators connect. In the DFG, each node is equivalent to an operator while the edges represent the relationship between these operators. Experience has proved that the higher the level of design optimization, the lower the design time in addition to higher efficiency, which is why the researchers are far more interested in optimization at higher levels of design than the lower levels. The complex, extensive, and discrete nature of the HLS problems has ranked them amongst the most complex problems in VLSI circuits engineering. Bearing this mind, using meta-heuristic and Swarm intelligence methods to solve high-level synthesis projects seems to be a favored option. In this paper, a heuristic method called Moth-Flame Optimization (MFO) has been used to solve the HLS problem in the design of digital transformer to find the optimal response. The MFO is a population-based heuristic algorithm that optimizes the problems using the laws of nature. The leading notion behind the MFO algorithm inspired from the moths’ movements and their instinctive navigation during the night. In the MFO algorithm, the moths are like chromosomes in the GA and like the particles in the PSO algorithm. In order to compare and prove the efficiency of the proposed method, it was applied on the test data with the GA-based method separately but with the same initial conditions. The comparative results along with the results of the GA-based method demonstrated that the proposed method exhibits a higher ability to provide the appropriate hardware structure and high-level synthesis of various types of transformers. Another outstanding feature of the proposed method is its high speed of finding an optimal response with an average of more than 20% greater than the GA based method. In order to build a VLSI circuit, several steps have to be taken from chip design to final construction. The first step in the synthesis of the integrated circuits is called high-level synthesis (HLS), in which a structural characteristic is obtained from a behavioral or algorithmic description. The resulting structural characteristic is equivalent to the one being considered in the behavioral description and it somehow represents the method for implementing the behavioral description so that several structural descriptions could be implementable for each behavioral description. Therefore, depending on the intended use, the characteristic will be selected that outperforms the others. The main purpose of the HLS is to optimize the power consumption, the chip occupied area and delay and this is fulfilled by selecting the appropriate number of operating units and how they are implemented to the operators. This is generally accomplished through a graph analysis called the data flow graph (DFG) which is a graphical representation of the type and how the operators connect. In the DFG, each node is equivalent to an operator while the edges represent the relationship between these operators. Experience has proved that the higher the level of design optimization, the lower the design time in addition to higher efficiency, which is why the researchers are far more interested in optimization at higher levels of design than the lower levels. The complex, extensive, and discrete nature of the HLS problems has ranked them amongst the most complex problems in VLSI circuits engineering. Bearing this mind, using meta-heuristic and Swarm intelligence methods to solve high-level synthesis projects seems to be a favored option. In this paper, a heuristic method called Moth-Flame Optimization (MFO) has been used to solve the HLS problem in the design of digital transformation to find the optimal response. The MFO is a population-based heuristic algorithm that optimizes the problems using the laws of nature. The leading notion behind the MFO algorithm inspired from the moths’ movements and their instinctive navigation during the night. In the MFO algorithm, the moths are like chromosomes in the GA and like the particles in the PSO algorithm. In order to compare and prove the efficiency of the proposed method, it was applied on the test data with the GA-based method separately but with the same initial conditions. The comparative results along with the results of the GA-based method demonstrated that the proposed method exhibits a higher ability to provide the appropriate hardware structure and high-level synthesis of various types of transforms. Another outstanding feature of the proposed method is its high speed of finding an optimal response with an average of more than 20% greater than the GA based method.