Hierarchical parametric test metrics estimation: A ΣΔ converter BIST case study
نویسندگان
چکیده
In this paper we propose a method for evaluating test measurements for complex circuits that are difficult to simulate. The evaluation aims at estimating test metrics, such as parametric test escape and yield loss, with parts per million (ppm) accuracy. To achieve this, the method combines behavioral modeling, density estimation, and regression. The method is demonstrated for a previously proposed Built-In Self-Test (BIST) technique for Σ∆ Analog-to-Digital Converters (ADC) explaining in detail the derivation of a behavioral model that captures the main nonidealities in the circuit. The estimated test metrics are further analyzed in order to uncover trends in a large device sample that explain the source of erroneous test decisions.
منابع مشابه
BIST for discrete - time Sigma - Delta ADC
Scientific Test and diagnosis for mixed-signal/RF integrated devices, design-for-test, behavioral and statistical modeling Fields of expertise Microelectronics, control, statistics Know-how Test metrics estimation, machine-learning-based test, parameter estimation for test and control, diagnosis, mixed-signal/RF design-for-test Industrial transfer Techniques of integrated test for analog-to-dig...
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