Cascade Ballroom M - 01 A Robust Parasitic - Insensitive Successive Approximation Capacitance - to - Digital
نویسندگان
چکیده
We present a 500-MHz, ultra-low-power phase-locked loop (PLL) realized with the near-threshold supply voltage of 0.4 V in 65-nm CMOS technology. Our PLL employs a new charge pump (CP) circuit structure that can greatly reduce CP up/down current mismatch and their variation with voltage-controlled oscillator (VCO) control voltages. The PLL consumes only 127.8 μW, which corresponds to power efficiency of 0.256 mW/GHz. Index Terms — Automatic frequency calibration (AFC), charge pump, current mismatch, current variation, nearthreshold voltage (NTV), phase-locked loop (PLL), ultra-low power, ultra-low voltage (ULV).
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