Design and Implementation of Parallel CRC Generation for High Speed Application

CRC is playing a main role in the networking environment to detect the errors. With challenging the speed of transmitting data to synchronize with speed, it is essential to increase speed of CRC generation. Most electronics engineers are familiar with the cyclic redundancy check (CRC).In the era of high speed data transmission, there requires a lot of accuracy for the message to be sent correctly to the receiver. And to check whether the message is correctly sent or not, an error detection technique called “CRC generation and check” is used. This technique informs the sender if any error is occurred. We know that it is widely used in communication protocols to detect bit errors and that it is essentially a remainder of the modulo-2long division operation. As a vital method for dealing with data errors usually the hardware implementation of CRC computations is based on the linear feedback shift registers (LFSRs), which handle the data in a serial way. As the serial calculation of the CRC codes cannot achieve a high throughput. Whereas in parallel CRC calculations can significantly increases the throughput of CRC computations. Mutants of CRCs are used in applications like CRC-16BISYNC protocols, CRC32 in Ethernet for error finding, CRC8 in ATM, CRC-CCITT in X-25 protocols, disk storage, SDLC, and XMODEM. This paper represents 64-bits parallel CRC architecture. The overall design is functionally simulated using Xilinx ISE Simulator.For the detection of the error in the received message; the CRC-bits are appended to the received message and then the „ExclusiveOR‟ing is performed by the polynomial. This gives us the generated CRC number, which is later used in the „CRC check method‟, is used to verify the accuracy of data transmission.