Buffered Banks in Multiprocessor Systems

A memory design based on logi cal banks is analyzed for shared memory mul tiprocessor systems In this design each phys ical bank is replaced by a logical bank consist ing of a fast register and subbanks of slower memory The subbanks are bu ered by in put and output queues which substantially re duce the e ective cycle time when the refer ence rate is below saturation The principal contribution of this work is the development of a simple analytical model which leads to scaling relationships among the e ciency the bank cycle time the number of processors the size of the bu ers and the granularity of the banks These scaling relationships imply that if the interconnection network has su cient bandwidth to support e cient access using high speed memory then lower speed memory can be substituted with little additional inter connection cost The scaling relationships are shown to hold for a full datapath vector sim ulation based on the Cray Y MP architecture The model is used to develop design criteria for a system which supports independent reference streams and the performance of this system is evaluated by simulation over a range of loading conditions keywords Bu ered memories logical mem ory banks memory con icts vector proces sors Cray Y MP