Design of a DSP Unit for 32-bit Embedded EISC Microprocessor

In this paper we designed a low hardware cost and fast DSP unit for 32-bit embedded EISC (Expanded Instruction Set Computer) microprocessor. The DSP unit operates as a functional unit of a integer core. This architecture can reduce the hardware cost and control easily the pipeline of the processor. The MAC/MAS unit was designed using hybrid radix-4/radix-8 Booth algorithm to reduce the hardware cost. All of the DSP instructions except DSP XY memory MAC/MAS instructions are executed in single cycle and have single cycle throughput. This DSP unit was modeled in Verilog HDL and synthesized with 0.35 μm standard cell libraries after verifications. Occupied area is 21,850 equivalent gates. It operates at 63 MHz clock speed under the worst-case conditions.