Area efficient 0 . 18 um Cmos phase frequency detector for high speed Pll

Two phase frequency detectors (PFDs) are proposed in this paper that can overcome the speed and area limitations of conventional PFD. The AND gate based PFD uses 22 transistors. It consumes 161.41uW power when operating at 50MHz clock frequency with 1.8V supply voltage. The NOR gate based PFD uses 20 transistors and preserves the main characteristics of conventional PFD. It consumes 96.67uW power at 50MHZ with 1.8V supply. The designs are implemented using 0.18um cmos process in Tanner 13.0v and can operate up to 1GHz frequency. These can be used in PLL for high speed applications. Index Terms – phase frequency detector, phase locked loop, CMOS integrated circuits, tanner