An Area Efficient 4Gb/s 3-Tap Decision Feedback Equalizer with Current-Integrating Summer

of the Thesis An Area Efficient 4Gb/s 3-Tap Decision Feedback Equalizer with Current-Integrating Summer by Chen Zhang Master of Science in Electrical and Computer Engineering Northeastern University, April 2016 Prof. Yong-Bin Kim, Adviser As the requirement of wire line applications increases, the demand for higher data transmission bandwidth is continuously exploding. While the on-chip speed has led to a growing interest in developing faster I/O for chip-to-chip and backplane communication, bandwidth limitation has not shown dramatic improvement over the years. Consequently, it presents great challenges to achieving multi-gigabits per second signaling rate. The inherent undesirable electrical characteristics of channel and issues induced by neighboring channels such as crosstalk severely degrade the transmitted signal. According to prior research works, Intersymbol Interference (ISI) is the dominant noise for high-speed backplane transmission, which makes one data bit broaden to greater than one Unit Interval (UI). High possibility of error is shown in data detecting at receiver due to the interference between the current data bit and the accumulated “tail”s which come from its preceding bits. Nowadays, there are number of equalization methods that are applied to both transmitter and receiver to eliminate the effect of ISI. Among these equalizers, Decision Feedback Equalizer (DFE) is the most widely-used discrete-time equalizer, which stores and feeds back the decisions it has made for the previous bits and subtracts the ISI of these stored bits from the current signal. The DFE shows a good advantage that it reduces signal distortion without amplifying noise or crosstalk. In this research, an area efficient decision feedback equalizer with a new current-integrating summer in standard CMOS 180nm technology node is designed and simulated in Cadence. Since the feedback timing constraint for the first tap is one of the greatest challenge in DFE design, first-tap speculative architecture is commonly used to relax this timing margin. For conventional first-tap speculative half-rate DFE, four parallel paths have exactly the same hardware and the main part of summer in two speculative paths is redundant. In order to optimize the structure, a new currentintegrating summer with switched-capacitors is proposed. Unlike the conventional one, the proposed x summer separates the first speculative tap which allows two parallel paths for speculation to be driven by a single summer instead of two. The proposed DFE consumes 17.4mW with 1.8V supply voltage when equalizing 4Gb/s data passed over a channel with 28dB loss at 2GHz. Simulation result shows that a horizontal 40% eye opening at BER less than 10−6 is derived.