Design of Soft Error Tolerant Logic Circuits

We present two novel circuit design techniques that effectively reduce the impact of radiation-induced single event transients (SET) on logic circuits. Both techniques can be applied to large CMOS designs and have been verified by a recently developed soft error rate analysis (SERA) methodology [3]. Rapid scaling of integrated circuit process technology has resulted in significant improvements in power consumption and throughput. However, reduced feature sizes and voltages make current and future integrated microsystems more vulnerable to soft errors due to alpha particles, high energy cosmic ray neutrons, and neutron induced B fission [1], [2]. Prior research has shown that the soft errors caused by radiation events, if uncorrected, result in a failure rate higher than all the other reliability mechanisms combined [4]. Circuit level hardening techniques have been applied to sequential logic circuits in prior work, such as dual interlocked storage cell (DICE) [5], Whitaker design [6], and Barry/Dooley design [7], [8]. These designs aim to protect the bits stored in bistable elements in the data retention mode. Other sequential circuit designs [9], [10] can block a fraction of the single event transients (SET) propagation from the logic. Such design styles will typically require delayed versions of clock or data signals, which results in drastic imapact on performance when the SET duration becomes large or when multiple SETs overlap with one another. The first design technique aims to reduce transient generation and propagation within the logic gate network, rather than blocking it after its generation and propagation. This design style can be employed in both static and dynamic CMOS combinational circuits, and does not require any passive elements such as resistors or capacitors. A static circuit designed in the proposed style has two output ports while a dynamic circuit has one. This design style achieves SET mitigation by incorporating two techniques simultaneously: 1) placing transistors that are closest to the output terminals in isolated wells and tying their body terminals to the corresponding source terminals. The resulting low electric fields across the drain-body and source-body junctions significantly weaken the charge collection efficiency. 2) attenuating SETs caused by charge collection near other transistors outside the isolated wells via voltage division. A dual output soft error tolerant inverter is compared with a conventional inverter in Fig. 1. The generation and propagation of a SET in inverter chain circuits are simulated and results are shown in Fig. 2. We assume in the circuit simulations that there is a particle strike on the n-type drain at the first inverter output at t = 300ps, and one on the p-type drain at the first inverter output at t = 800ps. Note that such an event sequence is for illustration purposes only and that the probability of such an event sequence is very low in practice due to the low particle flux and small drain area. It is clear from the waveforms in Fig. 2(a) that the generated SET in an inverter chain circuit composed of conventional inverters, if large enough in both magnitude and duration, could propagate down the logic chain with little or even no attenuation. This SET can have a detrimental effect on the reliability of a system if it arrives at a state node without being detected and corrected. On the other hand, the waveforms in Fig. 2(b) shows that only the output ports of the inverter under direct hit are adversely affected by the particle strike.