Why Can’t DFT Totally Eliminate Functional Test?
نویسنده
چکیده
Growing complexity of IC test issues demand using multiple approaches that complement each other in order to achieve cost effective solutions. As target IC size (i.e. equivalent number of logic gates) increases there is an obvious problem due to increased computational effort that is needed to generate test vectors. From a purely algorithmic point of view, it should be obvious that Design for Testability (DFT) is our best weapon for generating test vectors with high test coverage. Technological advances have made traditional reasons (excuses!) for not implementing adequate DFT become invalid. Thus, whereas additional gates are needed for implementing scan (internal or boundary scan) the relative cost of such gates have been decreasing rapidly, almost to the point of becoming not worth mentioning at all.
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