Implementation of Cryptographic Processor using Vedic Multiplier for High Speed Pairing

Pairings are attractive and competitive cryptographic primitives for establishing various novel and powerful information security schemes. This paper presents a flexible and high-performance processor for cryptographic pairings over pairing-friendly curves at high security levels. In this design, hardware for Fp2 arithmetic is optimized to accelerate the pairing computation, and especially a combined modular multiplier which is based on the 16-bit vedic multiplier, which implements (AB + CD) based on Montgomery method, is proposed. This combined multiplier has the data path delay close to that of a single multiplier implementing (AB) but saves area cost compared with two single multipliers. The Design I of the proposed processor is the first fabricated chip for pairing cryptography. For the comparison of results of our design with previous designs we used Xilinx tool.