Embedded Code Generation from High-level Heterogeneous Components. (Génération du Code Embarqué a partir de Composants de Haut-niveau Hétérogènes)

The work described in this thesis is done in the context of a long term effort at VERIMAG laboratory to build a complete model based tool-chain for the design and implementation of embedded systems. We follow a layered approach that distinguishes the application level from the architectural/implementation level. The application is described in a high-level language that is independent of implementation details. The application is then mapped to a specified architecture using a number of techniques so that the desired properties of the high level description are preserved. In this thesis, the application is described in SIMULINK/STATEFLOW, a wide-spread modeling language that has become a de-facto standard in many industrial domains, such as automotive. At the architectural level we consider single-processor, multi-tasking software implementations. Multi-tasking means that the application software is divided into a number of processes that are scheduled by a real-time operating system, according to some preemptive scheduling policy, such as static-priority or earliest deadline first. Between these two layers we add an intermediate representation layer, based on the synchronous language LUSTRE, developed at VERIMAG for the last 25 years. This intermediate layer permits us to take advantage of a number of tools developed for LUSTRE, such as simulators, model-checkers, test generators and code generators. In a first part of the thesis, we study how to translate automatically SIMULINK/STATEFLOW models into LUSTRE. For SIMULINK this is mostly straightforward, however it still requires sophisticated algorithms for the inference of type and timing information. The translation of STATEFLOW is much harder for a number of reasons; first STATEFLOW presents a number of semantically “unsafe” features, including non-termination of a synchronous cycle or dependence of semantics on the graphical layout. Second, STATEFLOW is an automata-based, imperative language, whereas LUSTRE is a dataflow language. For the first set of problems we propose a number of statically verifiable conditions that define a “safe” subset of STATEFLOW. For the second set of problems we propose a set of techniques to encode automata and sequential code into dataflow equations. In the second part of the thesis, we study the problem of implementing synchronous designs in the single-processor multi-tasking architecture described above. The crucial issue is how to implement inter-task communication so that the semantics of the synchronous design are preserved. Standard implementations, using single buffers protected by semaphores to ensure atomicity, or other, lock-free, protocols proposed in the literature do not preserve the synchronous semantics. We propose a new buffering scheme that preserves the synchronous semantics and is also lock-free. We also show that this scheme is optimal in terms of buffer usage.