Design and Synthesis of 32 Bits Linear Feedback Shift Registers Architecture with Power Optimization

LFSR based PN number generating technique is used for various cryptography applications for designing with various encoder and decoder architecture. It is used for getting efficient result. Modern field programmable gate arrays (FPGAs) include the resources needed to design efficient LFSR structures. LFSR are used for implementation any logic functions for faster prototype development. It is necessary to implement the existing design of LFSR on FPGA to test and simulation and synthesis result between different lengths. The total no of random state depend on the feedback polynomial. It is a simple counter with count maximum of using feedback polynomial. In this paper power optimized upto 25.9% in FPGA by implementation of 32-bit LFSR & also compared with 8-bit and 16-bit LFSR.