Minimum Inserted Buffers for Clock Period Minimization

Placement For Clock Period Minimization

A linear program is used to direct the placement of Standard Cells such that the clock period is minimized. Constraints upon the logic path delays and the clock signal arrival times at the flipflops allow multiple signals, corresponding to several clock cycles, to exist simultaneously on the logic signal paths during operation. The linear program constraints relate the clock period to the maxim...

High Performance Buffered X-architecture Zero-skew Clock Tree Construction with via Delay Consideration

As VLSI technology advances into nanometer dimensions, clock routing becomes a limiting factor in determining chip performance. To deal with the challenge, X-architecture has been proposed and widely applied in routing field because it contributes more improvements in terms of the clock delay, wirelength, and power consumption than general Manhattan-architecture. This work proposes an X-archite...

Achieving the Shortest Clock Period byInserting the Minimum Amount of

The performance of a circuit depends on its clock period. The shorter a valid clock period is, the better the performance is. The clock period is tightly related to the diierence between the longest propagation delay and the shortest propagation delay from primary inputs to primary outputs. The objective of this paper is to minimize the amount of delay inserted while achieving the shortest cloc...

Clock Period Minimization of Semi-Synchronous Circuits by Gate-Level Delay Insertion

A semi-synchronous circuit is a circuit in which every register is ticked by a clock periodically, but not necessarily simultaneously. A feature of semi-synchronous circuits is that the minimum delay between registers may be critical with respect to the clock period of the circuit. In this paper, we discuss a delay insertion method which makes such a semi-synchronous circuit faster. The maximum...

Clock Skew Minimization in Multiple Dynamic Supply Voltage with Adjustable Delay Buffers Restriction