Performance Driven Inter-FPGA Synchronization Algorithm for Multi-FPGA Simulation Accelerator with Event Time-multiplexing Bus
نویسنده
چکیده
Simulation is the most viable solution for the functional verification of SoC. The acceleration of simulation with multi-FPGA is a promising method to comply with the increasing complexity and large gate capacity of SoC. The most time-consuming factor of multi-FPGA simulation accelerator is synchronization time between simulator and multi-FPGA system. Time-multiplexing of interconnection wires is the inevitable solution to solve the pin limitation problem that limits the gate utilization of FPGAs and speed of the multi-FPGA simulation accelerator. This paper proposes a performance driven interFPGA signal synchronization algorithm for multi-FPGA systems with time-multiplexed interconnection in a simulation accelerator. The proposed synchronization algorithm optimizes synchronization time for FPGAs by event-based signal synchronization on ETB (Event Time-multiplexed Bus). The circuit partitioning considering the signal probability, net dependency reduction and efficient net clustering for reducing addressing overhead minimize synchronization time. Experiments shows that inter-FPGA synchronization time using ETB is 8%∼18% of traditional algorithms.
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