Low Power Design of Digital Systems Using Energy Recovery Clocking and Clock Gating

Energy recovery clocking has been demonstrated as an effective method for reducing the clock power. However, in this method the conventional square wave clock signal is replaced by a sinusoidal clock generated by a resonant circuit. Such a modification in clock signal prevents application of existing clock gating solutions. In this paper, we propose clock gating solutions for energy recovery clocking by gating the flip-flops or the clock generator. According to simulations results in 0.25um CMOS technology, applying our clock gating to the energy recovery clocked flip-flops reduces their power by 1000X in the idle mode with negligible power and delay overhead in the active mode. Applying the proposed clock gating technique to a system of 1000 flip-flops with idle mode probability and data switching activity of 50%, reduces the total power by 47%. We also propose negative edge triggering solution for the energy recovery clocked flip-flops. I certify that the Abstract is a correct representation of the content of this thesis. _________________________ _____________ Chair, Thesis Committee Date v ACKNOWLEDGEMENTS I would like to thank my advisor Dr. Hamid Mahmoodi for his invaluable advice and support towards the completion of my thesis. I would like to thank my engineering department for providing me the resources required for completing my project. I would like to thank Dr. Ying Chen for her timely feedbacks. I would like to thank my family and friends for their support.