Clock Distribution in RNS-based VLSI Systems

Clock distribution networks synchronize the flow of data in digital systems, and the features of the clock signal affect system performance and reliability. The great advances in integration levels and speed requirements in actual digital systems lead to enormous complexity in synchronization. Differences in delay of clock signals along clock paths, due to different lengths or active elements such buffers, cause loss of performance and poor reliability. However, a perfect synchronization leads to a simultaneously triggering of great amount of devices and, thus, large current demands. This paper presents a new scheme for clock distribution in VLSI systems that avoids both skew and large current demand related problems. Different skewed clock signals synchronize different independent channels in a RNS-based system. This new strategy has been simulated over a three-stage decimation CIC filter, resulting in a diminution of current spikes and current change rate with no significant increase of power consumption. Key-Words: Clock, Clock Distribution, RNS, Synchronization.