Static scheduling of instructions on micronet-based asynchronous processors
نویسندگان
چکیده
This paper investigates issues which impinge on the design of static instruction schedulers for micronet-based asynchronous processor (MAP) architectures. The micronet model exposes both temporal and spatial concurrency within a processor. A list scheduling algorithm is described which has been optimised with MAP-speciic heuristics. Their performance on some program graphs are presented and conclusions are drawn on the suitability of MAP as targets for ILP compilers.
منابع مشابه
Static Scheduling of Instructions on Micronet-based Asynchronous Processors - Advanced Research in Asynchronous Circuits and Systems, 1996. Proceedings., Second International S
This paper investigates issues which impinge on the design of static instruction schedulers for micronetbased asynchronous processor (MAP) architectures. The micronet model exposes both temporal and spatial concurrency within a processor. A list scheduling algorithm is described which has been optimtsed with MAP-specific heuristics. Their performance on some program graphs are presented and con...
متن کاملScheduling Instructions with Uncertain Latencies in Asynchronous Architectures
This paper addresses the problem of scheduling instructions in micronet-based asynchronous processors (MAP), in which the laten-cies of the instructions are not precisely known. A PTD scheduler is proposed which minimises true dependencies, and results are compared with two list schedulers-the Gibbons and Muchnick scheduler, and a variation of the Balanced scheduler. The PTD scheduler has a low...
متن کاملScheduling for ILP in the ‘Processor-as-a-Network’
This paper explores the idea of the processor as an asynchronous network, called the micronet, of functional units which compute concurrently and communicate asynchronously. A micronet-based asynchronous processor exposes spatial as well as temporal concurrency. We analyse the performance of the ‘processor-as-a-network’ by comparing three scheduling algorithms for exploiting Instruction Level P...
متن کاملMicronet-based CISC Architectures
We have in the past investigated the design and implementation of micronet-based architectures of the scalar[AR94], superscalar[AM99], VLIW[AS97] and Multithreaded[AHKR01] kind, which were all based on a RISC-like instruction set. In this paper, we present a preliminary design, based around a micronet core, of an asynchronous Complex Instruction Set Computer (CISC) architecture. A TRANSLATOR mo...
متن کاملInstruction-level Parallelism in Asynchronous Processor Architectures
The Micronet-based Asynchronous Processor (MAP) is a family of processor architectures based on the micronet model of asynchronous control. Micronets distribute the control amongst the functional units which enables the exploitation of ne-grained concurrency, both between and within program instructions. This paper introduces the mi-cronet model and evaluates the performance of micronet-based d...
متن کامل