Analysis and Mitigation of Cmos Gate Leakage
نویسندگان
چکیده
Conventional leakage reduction techniques focus primarily on sub-threshold leakage mitigation, while neglecting the effect of gate leakage current. This work focuses on understanding gate leakage current and developing circuit techniques for total leakage minimization. We present an efficient technique for gate leakage of CMOS circuits. Input vector control and circuit reconfiguration techniques for total leakage minimization of static and dynamic circuits are presented. Finally design guidelines for optimal device size selection for stacked sleep devices in an enhanced MTCMOS configuration are presented.
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