Analysis of Gate-Bias-Induced Heating Effects in Deep-Submicron ESD Protection Designs
نویسندگان
چکیده
This paper presents a detailed investigation of the degradation of electrostatic discharge (ESD) strength with high gate bias for deep-submicron salicided ESD protection nMOS transistors, which has significant implications for protection designs where high gate coupling occurs under ESD stress. It has been shown that gate-bias-induced heating is the primary cause of early ESD failure and that this impact of gate bias depends on the finger width of the protection devices. In addition, it has been established that substrate biasing can effectively alleviate the adverse impact of the gate bias and can improve ESD strength despite the gate-coupling level. Improved understanding of ESD behavior for advanced devices under high gate-coupling conditions can extend design capabilities of protection structures.
منابع مشابه
Analysis of Nonuniform ESD Current Distribution in Deep Submicron NMOS Transistors
This paper presents a detailed study of the nonuniform bipolar conduction phenomenon under electrostatic discharge (ESD) events in single-finger NMOS transistors and analyzes its implications for the design of ESD protection for deep-submicron CMOS technologies. It is shown that the uniformity of the bipolar current distribution under ESD conditions is severely degraded depending on device fing...
متن کاملImpact of Gate-to-Contact Spacing on ESD Performance of Salicided Deep Submicron NMOS Transistors
Electrostatic discharge (ESD) failure threshold of NMOS transistors is known to degrade with the use of silicided diffusions owing to insufficient ballast resistance, making them susceptible to current localization, which leads to early ESD failure. In general, the gate-to-contact spacing of salicided devices is known to have little impact on their ESD strength. However, experimental results pr...
متن کاملCapacitor-couple ESD protection circuit for deep-submicron low-voltage CMOS ASIC
Capacitor-couple technique used to lower snapbacktrigger voltage and to ensure uniform ESD current distribution in deep-submicron CMOS on-chip ESD protection circuit is proposed. The coupling capacitor is realized by a poly layer right under the wire-bonding metal pad without increasing extra layout area to the pad. A timing-original design model has been derived to calculate the capacitor-coup...
متن کاملInvestigation of Gate to Contact Spacing Effect on ESD Robustness of Salicided Deep Submicron Single Finger NMOS Transistors
ESD failure threshold of NMOS transistors is known to degrade with the use of silicided diffusions owing to insufficient ballast resistance, making them susceptible to current localization, which leads to early ESD failure. It is commonly believed that the gate-tocontact spacing of silicided devices has no impact on the ESD strength. However, experimental results presented in this paper show th...
متن کاملNon-uniform Bipolar Conduction in Single Finger NMOS Transistors and Implications for Deep Submicron ESD Design
This paper presents a detailed study of the non-uniform bipolar conduction phenomenon in single finger NMOS transistors and analyses its implications for deep submicron ESD design. It is shown that the uniformity of lateral bipolar triggering is severely degraded with device width (W) in advanced technologies with silicided diffusions and low resistance substrates, and that this effect can only...
متن کامل