A Generalized Minimum Dynamic Power and High-Speed Design Method for CMOS Circuits

We formulate a linear program (LP) to simultaneously minimize the dynamic power and overall delay of a CMOS circuit. To eliminate all glitches either without or with minimal number of delay bu ers, a CMOS gate is assumed to have adjustable input to output delays for each input. Since these delays are not independent, a transistor sizing problem would require very complex non-linear optimization. We solve the problem in three steps. First, CMOS gates are analyzed to determine the realizable maximum di erential input delay, ub, for the device technology being used. Second, an LP assumes the gate input and output delays as independent variables and determines them for all gates. This LP satis es (1) glitch elimination conditions and the realizability constraint (ub) for all gates, and (2) the speci ed overall delay for the circuit. The total number of constraints in our LP is a linear function of the circuit size. Third, all gates are designed with the delays determined by the LP. As a sample result, using ub = 10 when we designed the c1355 benchmark circuit specifying a large overall delay, a zero bu er design was obtained. It consumed 33% power and had three times the overall delay as compared to an unoptimized design. When the overall delay was constrained not to increase, the low-power design required 64 delay bu ers and consumed 37% power.