A New Low Voltage CMOS 1-Bit Full Adder for Low-Power Applications
نویسنده
چکیده
In this paper, a new low-voltage low-power CMOS 1-bit full adder circuit is proposed. The proposed full adder can provide a full voltage swing at a low supply voltage and offers superior performance in both power and speed than the conventional full adder, the transmission full adder, and the recent low-voltage full adder. Based on the simulation results performed by HSPICE, the new low-voltage design consumes a minimal power and has a minimal power-delay product in TSMC 0.35um process as the supply voltage varies from 3.3V to 2V. Besides, this new cell is demonstrated to consume the minimal power as adopted in both a 4*4 bit carry-save array adder, and a 4*4 bit pipelined carry-save array adder. Key-Words: Low-Voltage, Low-Power, Full-Adder, Carry-Save Adder, Pipeline, CMOS
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