An 80Gbps FPGA Implementation of a Universal Hash Function based Message Authentication Code

We developed an architecture optimization technique called divide-and-concatenate and applied it to a cryptographic message authentication code (MAC). This is based on two key observations: (i) The area of a multiplier and associated data path decreases quadratically and their speeds increase gradually as their operand size is reduced. (ii) Two w-bit universal hash function data paths (each with collision probability 2) can be concatenated to construct a 2w-bit universal hash function data path (with a collision probability 2) [3]. In the proposed approach we divide a 2w-bit data path (with collision probability 2) into two w-bit data paths (each with collision probability 2) and concatenate their results to construct an equivalent 2w-bit data path (with a collision probability 2). We applied the divide-and-concatenate technique on NH universal hash function that uses multiplications and additions. We prototyped NH hash based message authentication code UMAC architecture with a collision probability 2 that uses four equivalent 8-bit divide-and-concatenate NH hash data paths on a Xilinx XCV1000-6 Field Programmable Gate Array (FPGA). This implementation yielded a throughput of 79.2 Gbps with only 3840 FPGA slices. When compared to the 100% overhead associated with duplicating a straightforward 32-bit pipelined NH hash data path, the divide-and-concatenate approach yields a 94% increase in throughput with only 40% hardware overhead. Furthermore, this is an order of magnitude faster than existing hardware implementations of MD5 and SHA1 MACs. If accepted for presentation, we will demonstrate our 80Gbps FPGA implementation at the Design Automation Conference.