A Modified Scale Free CORDIC Architecture to Improve the Speed

In spite of several modified versions proposed, there is a huge demand for an efficient implementation of CORDIC in signal processing applications. Various methods proposed for CORDIC have their own drawbacks either in range of functionality or complexity. This paper presents speed optimized scale-free CORDIC in order to be mainly used in signal processing applications such as FFT and DCT etc.The proposed CORDIC provides enough flexibility to be implemented in signal processing applications to carry out vector rotation operation with required accuracy. The system uses less number of slices with increase in speed when compared with conventional version upon implementing on Xilinx virtex 5. The sine and cosine waveforms of the pipelined design is also shown for verification.