Deep Submicron VLSI Floorplanning Algorithm

In deep submicron VLSI designs, cross capacitance between adjacent wires becomes the dominant factor in determining chip performance and power consumption. Consequently, traditional floorplanning algorithms, which typically optimize for die area and ignore wire congestion, become inadequate in deep submicron era. Based on a stochastic congestion model, we propose a floorplanning algorithm that optimizes for chip power consumption and performance. A floorplanning prototype was built to prove the effectiveness of the algorithm. We have verified the prototype with MCNC benchmarks, and the results are very promising.