A Modified 8-Transistor SRAM Cell Design with High Stability and Low Power Applications

SRAM occupies two-third area of VLSI chips, therefore it dominates the total power consumption. To enhance the performance of these chips, SRAM cell should meet the requirement of lesser power consumption. This paper presents a new 8T SRAM cell that is efficient in Dynamic power consumption in Write mode and Leakage power consumption when compared with referred 9T SRAM cell and standard 6T SRAM cell. The design is simulated in 45-nm CMOS technology that results 18.6% reduction in Dynamic power consumption during Write mode and 28.4 % reduction in Leakage power consumption as compared to referred 9T SRAM cell. When compared with standard 6T SRAM cell this new 8T SRAM cell results 20.1 % reduction in Dynamic power consumption during Write mode and 18.1 % reduction in Leakage power consumption.