Transient-Enhanced Diffusion in Shallow-Junction Formation

Current methods for forming junctions in the source and drain regions of complementary metaloxide semiconductor (CMOS) transistor circuits use low-energy ion implantation and rapid thermal annealing (RTA). Spike annealing, with fast ramping and short dwell time at maximum temperature, has been shown to be advantageous for shallow-junction formation. Diffusion and electrical activation of implanted B, P, and As dopants in crystalline Si are examined in this work. During annealing, these dopants experience an enhanced diffusion when excess Si interstitials are present. For implanteddopant species, excess Si interstitials evolve from the residual implant damage until the damage is annealed out. The resulting enhanced diffusion is, thus, transient and is denoted transient-enhanced diffusion (TED). In the case of boron, excess interstitials can also be generated by the formation of a boron-silicide phase if the surface boron concentration is high enough. The phenomenon is referred to as boron-enhanced diffusion (BED) and occurs for both ion-implanted B and for a B film deposited on the surface. Although enhanced diffusion of any kind is unfavorable for shallow-junction formation in advanced transistor designs, grain-boundary-enhanced diffusion is beneficial in gate-electrode formation from implanted polycrystalline Si. The high temperatures reached by spike annealing are also advantageous for increasing the concentration of dopants in solid solution.