A generalized methodology for lower-error area-efficient fixed-width multipliers
نویسندگان
چکیده
Abstract In this paper, we extend our generalized methodology for designing lower-error area-efficient fixed-width two’s-complement multipliers that receive two s -bit numbers and produce an s -bit product. The generalized methodology involving four steps results in several better error-compensation biases. These better error-compensation biases can be easily mapped to lower-error fixed-width multipliers suitable for VLSI realization.
منابع مشابه
Design of the Lower Error Fixed-Width Multiplier and Its Application
This brief develops a general methodology for designing a lower-error two’s-complement fixed-width multiplier that receives two -bit numbers and produces an -bit product. By properly choosing the generalized index, we derive the better error-compensation bias to reduce the truncation error and then construct a lower error fixed-width multiplier, which is area efficient for VLSI implementation. ...
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