Characterization of Variability in Deeply-Scaled Fully Depleted SOI Devices

Scaling of CMOS technology into the deep submicron regime gives rise to process variability, which in turn compromises circuit yield. One of the main sources of variability is random dopant fluctuation (RDF) in the channel. Fully Depleted Silicon on Insulator technology has been proposed as a promising alternative to bulk CMOS, due to it’s undoped channel which reduces RDF, as well as due to its better electrostatic control of the channel. A testchip for measurement and analysis of variability in a 22nm FDSOI process has been designed. Among other experiments, the tetstchip features an array of 11x11 tiles with variability measurement structures. Each tile contains circuits to measure IV and CV device characteristics, RO frequencies and resistor values. Scan chains and multiplexing are employed to enable analysis of a large number of DUTs with a limited pad count. The goal of this testchip is to characterize variability in FDSOI. This will be achieved by extracting systematic and random variation data from specifically designed test structures. The focus of this testchip is to decouple different sources of random variation in order to electrically measure line edge roughness and silicon thickness variation due to surface roughness, characterize the effects of source and drain doping, and quantify the contribution of ground planes and back-biasing in FDSOI variability.