13th Int'l Symposium on Quality Electronic Design
نویسندگان
چکیده
Experimental results of an active filter based onchip hybrid voltage converter are described in this paper. The area of the voltage converter is significantly less than the area of a conventional passive filter based DC-DC voltage converter or a low-dropout (LDO) regulator. Hence, the proposed circuit is appropriate for point-of-load voltage regulation for the noise sensitive portions of an integrated circuit. The performance of the circuit has been verified with Cadence Spectre simulations and fabricated with a commercial 110 nm CMOS technology. The area of the voltage regulator is 0.015 mm and delivers up to 80 mA of output current. The transient response with no output capacitor ranges from 72 ns to 192 ns. The advantages and disadvantages of an active filter based, conventional switching, linear, and switched capacitor voltage converters are compared. The proposed circuit provides a means for distributing multiple local power supplies across an integrated circuit while maintaining high current efficiency and fast response time within a small area.
منابع مشابه
13th Int'l Symposium on Quality Electronic Design
Bias temperature instability (among other problems) is a key reliability issue with nanoscale CMOS transistors. Especially in sensitive circuits such as sense amplifiers of SRAM arrays, transistor aging may significantly increase the probability of failure. By analyzing the Current Based Sense Amplifier circuit and Voltage-Latched Sense Amplifier circuit through HSPICE simulations, we observe t...
متن کامل13th Int'l Symposium on Quality Electronic Design
Three dimensional integrated circuits (3D ICs) built with through-silicon vias (TSVs) have smaller footprint area, shorter wirelength, and better performance than 2D ICs. However, the quality of 3D ICs is strongly dependent on TSV dimensions and parasitics. Using large TSVs may cause silicon area overhead and reduce the amount of wirelength reduction in 3D ICs. In addition, non-negligible TSV p...
متن کامل13th Int'l Symposium on Quality Electronic Design
The Network-on-Chip (NoC) is an enabling technology to integrate large numbers of embedded cores on a single die. Traditional multi-core designs based on the NoC paradigm suffer from high latency and power dissipation due to the inherent multi-hop nature of communication. The performance of NoC fabrics can be significantly enhanced by introducing long-range, low power, and high-bandwidth single...
متن کامل13th Int'l Symposium on Quality Electronic Design
A post-fabrication dual supply voltage (VDD) control (PDVC) of multiple voltage domains is proposed for a minimum operating voltage (VDDmin)-limited ultra low voltage logic circuits. PDVC effectively reduces an average VDD below VDDmin, thereby reducing the power consumption of logic circuits. PDVC is applied to a DES CODEC’s circuit fabricated in 65nm CMOS. The layout of DES CODEC’s is divided...
متن کامل13th Int'l Symposium on Quality Electronic Design
In modern VLSI circuits, a large number of clock buffers are inserted in clock distribution networks, which are significantly affected by process and power supply noise variations. The combined effect of process variations and power supply noise on clock skew and jitter is investigated in this paper. A statistical model of skitter, which consists of skew and jitter, is proposed. Clock paths wit...
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