DATE 2009 Workshop on 3D Integration

THE 2009 Design, Automation, and Test in Europe (DATE) conference, which took place in April in Nice, France, hosted a new workshop on 3D integration. The topic was vertical stacking of multiple silicon dies, interconnected by through-silicon vias, which is a promising technology. TSVs offer higher transistor density, faster interconnects, heterogeneous technology integration, and potentially lower cost and time-tomarket. What was unique about this workshop was that the topic was not only approached as a processing or packaging issue, but it was discussed from all angles: technology, architecture, design, automation, and test. The 3D integration workshop opened with a keynote address by Sitaram Arkalgud of Sematech, called ‘‘The Promise of Through-Silicon Vias.’’ This presentation gave a very well-structured overview of the possibilities, options, and challenges that TSV-based technologies offer. In a subsequent invited talk, Riko Radojcic of Qualcomm spoke on ‘‘Requirements for Design-for-3D Environment,’’ in which he described the needs for exploiting 3D technology in design automation. These needs range from high-level architecture exploration, including efficient thermal modeling, down to co-optimizing design and process technology. The main body of the workshop was formed by two sessions with three full-length paper presentations each. These papers covered topics as system applications in multimedia, ‘‘via first’’ and ‘‘via last’’ technologies, cost modeling, clock and power distribution over 3D interconnects, hierarchical cache design, and test strategies for 3D chips. Two lively poster sessions with a total of 22 posters offered attendees the opportunity to meet face-to-face with the presenters to discuss a wide variety of 3D topics. The day was closed with a panel session, led by Pol Marchal of IMEC, in which six panelists again considered 3D integration from all angles: technology, semiconductor equipment, system design, analog design, design automation, and test.