A Reconfigurable Multiplier Array For Video Image Processing Tasks, Suitable For Embedding In An FPGA Structure
نویسندگان
چکیده
Abstract This paper presents a design for a reconfigurable multiplier array. The multiplier is constructed using an array of 4 bit Flexible Array Blocks (FABs), which could be embedded within a conventional FPGA structure. The array can be configured to perform a number of 4n x 4m bit signed/unsigned binary multiplications. We have estimated that the FABs are about 35 times more efficient in area than the equivalent multiplier implemented using a conventional FPGA structure alone.
منابع مشابه
Configurable multiplier blocks for use within an FPGA
Abstract A new architecture is proposed for configurable blocks which can be used to construct a multiplier. An array of these blocks is capable of being configured to perform any 4m bits x 4n bits signed/unsigned binary multiplication. The blocks are designed to be embedded within a conventional FPGA structure to increase the functionality of the device by freeing valuable general reconfigurab...
متن کاملA Digit-Serial Structure for Reconfigurable Multipliers
This paper presents a design for combining reconfigurable multiplier array known as Flexible Array Blocks (FABs) and digit-serial techniques to implement arbitrary size multipliers with limited resources. Any 4Mx4N bit multipliers can be implemented. In-depth evaluation of the tradeoff between resources and performance is presented. The resulting design is suitable for embedding in heterogeneou...
متن کاملP2IP: A novel low-latency Programmable Pipeline Image Processor
This paper presents a novel systolic Coarse-Grained Reconfigurable Architecture for real-time image and video processing called PIP. The PIP is a scalable architecture that combines the low-latency characteristic of systolic array architectures with a runtime reconfigurable datapath. Reconfigurability of the PIP enables it to perform a wide range of image pre-processing tasks directly on a pixe...
متن کاملFPGA Implementation of JPEG and JPEG2000-Based Dynamic Partial Reconfiguration on SOC for Remote Sensing Satellite On-Board Processing
This paper presents the design procedure and implementation results of a proposed hardware which performs different satellite Image compressions using FPGA Xilinx board. First, the method is described and then VHDL code is written and synthesized by ISE software of Xilinx Company. The results show that it is easy and useful to design, develop and implement the hardware image compressor using ne...
متن کاملFPGA implementation of real-time human motion recognition on a reconfigurable video processing architecture
In recent years, automatic human motion recognition has been widely researched within the computer vision and image processing communities. Here we propose a real-time embedded vision solution for human motion recognition implemented on a ubiquitous device. There are three main contributions in this paper. Firstly, we have developed a fast human motion recognition system with simple motion feat...
متن کامل