Hardware Implementation of 16*16 bit Multiplier and Square using Vedic Mathematics

Multiplication and square are elementary mathematical operations extremely important for core computing process. Also exponentiation, the process of raising a base number to a power is an important operation in many numerical computations. To keep pace with the technology, high speed applications require faster methods of multiplication and Square architecture. This paper reports a new faster algorithm for multiplication and square based on ancient Indian mathematics, called Vedic Mathematics. The design for the architecture of 16*16 bit multiplier and square is proposed and described using VHDL hardware description language. The code description is simulated using ModelSim SE 5.7f and synthesized using ISE Xilinx 9.2i for the FPGA device Spartan XC3S500e-fg320, Speed Grade-4. The synthesis showed reduced time delay for the multiplier and square. The proposed design is also compared with other existing methods, resulting in improved efficiency in both speed and area.