Design of an Effective Pipeline FFT/IFFT Processor

This investigation proposes the novel radix-4 and radix-4 algorithms with the low computational complexities of the radix-16 and radix-64 algorithms and the low hardware requirement of the radix-4 algorithm. Base on the multiplierless radix-4 butterfly structure, the proposed radix-4 single-path delay feedback (R4SDF) design and radix-4 single-path delay feedback (R4SDF) design support the 4096-point FFT/IFFT computations. Moreover, the retrenched constant multiplier and eight-folded complex multiplier structures are adopted to decrease the multiplier cost and the coefficient ROM size with the complex conjugate symmetry rule and subexpression elimination technology. To further decrease the chip cost, a finite word-length analysis is provided to indicate that the proposed R4SDF and R4SDF architectures only require 14 and 13-bit internal word-length to achieve 40dB SNR performance in the 4096-point FFT/IFFT computation. The comprehensive comparison results indicate that the proposed R4SDF design has the smallest hardware cost and the highest hardware utilization among the tested architectures for the FFT/IFFT computation, and thus has the highest efficiency. The implementation results show that the proposed R4SDF and R4SDF based 4096-point pipeline FFT/IFFT processors only consumes 6.3725 and 5.985 mW@20 MHz at 1.2V supply voltage in TSMC 0.13 μm CMOS process. 1