Design and Synthesis of Reduced Delay BCD
نویسنده
چکیده
Arithmetic and memory address computation are performed using adder operations. Hence, design of adders form an important subset of electronic chip design functionality. Performance of BCD adders is to be considered with gate count, area, delay, power consumption. A new BCD adder design is attempted here to reduce the delay and thereby increasing the speed of response. BCD adder design is considered with respect to high speed addition requirement including multi operand addition, multiplication and division. The new architecture supports 64 bit and 128 bit operands and reduces the delay by adding parallelism.
منابع مشابه
Performance Analysis of Flagged BCD Adder and Pipelined BCD Adder
BCD Adder is the fundamental adder we learn in logic design and any basic electronics lab. Conventional BCD Adder what we generally know is not feasible for higher bits as they require more area and as they have more propagation delay for higher bit extension. For higher level application BCD design we require more efficient basic BCD block. So in this paper we proposed 2 types of BCD adders na...
متن کاملDesign of High-speed low power Reversible Logic BCD Adder Using HNG gate
Reversibility plays a fundamental role when computations with minimal energy dissipation are considered. In recent years, reversible logic has emerged as one of the most important approaches for power optimization with its application in low power CMOS, optical information processing, quantum computing and nanotechnology. This research proposes a new implementation of Binary Coded Decimal (BCD)...
متن کاملDesign of Low Power Cmos Logic Circuits Using Gate Diffusion Input (gdi) Technique
The Gate diffusion input (GDI) is a novel technique for low power digital circuit design. This technique reduces the power dissipation, propagation delay, area of digital circuits and it maintains low complexity of logic design. In this paper, the 4×1 Multiplexer, 8×3 Encoder, BCD Counter and Mealy State Machine were implemented by using Pass Transistors (PT), Transmission Gate (TG) and Gate Di...
متن کاملDESIGN of HIGH SPEED, LOW AREA, CARRY FLOW BCD ADDER in QCA
We can overcome the CMOS scaling problems with emerging Nanotechnology. In Nanotechnology the basic building block of digital design is QCA. The problem in design of decimal adders on Quantum dot cellular automata with reduction of QCA primitives is very limited. In this paper we present a BCD adder with less number of QCA primitives and it is compared with existing BCD adder designs. Our propo...
متن کاملFast Mux-based Adder with Low Delay and Low PDP
Adders, as one of the major components of digital computing systems, have a strong influence on their performance. There are various types of adders, each of which uses a different algorithm to do addition with a certain delay. In addition to low computational delay, minimizing power consumption is also a main priority in adder circuit design. In this paper, the proposed adder is divided into s...
متن کامل